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Nvidia Unveils Vera Rubin NVL72 Platform, Claiming Token Throughput Seven Times Higher Than Blackwell

Nvidia has unveiled the Vera Rubin NVL72 platform for AI acceleration, claiming its token throughput exceeds that of the Blackwell platform by sevenfold, while expanding its infrastructure ecosystem via NVLink Fusion technology.

September 17, 2026
Nvidia Unveils Vera Rubin NVL72 Platform, Claiming Token Throughput Seven Times Higher Than Blackwell

Nvidia has unveiled its new Vera Rubin NVL72 platform designed to accelerate AI workloads, claiming that the token throughput of this platform exceeds what was achieved with the previous Blackwell platform by seven times—a claim that requires independent verification and precise calibration before being benchmarked.

The new platform relies on an optimized memory and processing unit architecture and integrates NVLink Fusion technology, which enables interconnecting multiple chips in a unified structure with limited data transfer bottlenecks between units, thereby addressing one of the main obstacles to scaling large AI models that suffer from data transport congestion between processing units.

These announcements are of utmost importance in the context of rising demand for high-performance computing from major AI labs, especially in light of supply chain pressures and efforts by Google, Amazon, and Microsoft to develop competing in-house chips.

This announcement reinforces Nvidia's continued dominance in the AI chip market, although competitors point to verification gaps and actual delivery as the real test beyond marketing figures.

What do these terms mean?

Token Throughput: The number of text units that a model can process per second, serving as a key metric for the speed and efficiency of AI chips.

NVLink Fusion: An advanced interconnect technology developed by Nvidia that enables connecting a larger number of GPU chips in a single integrated structure at high data transfer speeds with minimal latency.

Architecture: The internal structural design of a processing chip, which determines how computational tasks are distributed and how memory and power are managed.

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